This invention relates generally to the field of integrated circuits and more particularly relates to a method and apparatus to inserting a programmable delay in dynamic circuits.
The endeavor for faster and faster circuits have reached remarkable milestones since their inception and coming of age during the past sixty years, especially logic circuits in connection with the development of computers. The beginning of the computer age was characterized by connecting vacuum tubes with large coaxial cables for wiring analog logic. If a new problem was to be solved, the cables were reconfigured. Today, coaxial cables have been replaced with high speed data buses; vacuum tubes have been replaced with high speed logic circuits whose transistors are fabricated from new semiconductor materials and designs, all of which are limited only by the laws of physics.
While much work has been done in the arrangement of parts of a computer by, e.g., bringing memory closer to the processor and incorporating cache memories, etc., the real determination of how fast or how slow a computer is is dependent upon the circuit elements at the electronic level. Transistors themselves have become faster and a major aspect of circuit design is fine-tuning the delays associated with numerous signals to make the circuit as fast as possible and yet still maintain spatial and heat dissipation requirements.
Delay simply refers to a signal not arriving when it is expected, whether it be a clock signal or a data signal. In fact, hardware delays are often intentionally inserted into a complex circuit design to synchronize the arrival or evaluation of a particular signal in one part of the circuit with another part of the circuit, or to synchronize the arrival of two signals. The insertion of intentional delays is a critical aspect of circuit design. The problem of the precision of the delay predicted by computerized design models versus the delay in the actual manufactured hardware is described by the term xe2x80x9chardware-to-model correlation.xe2x80x9d If the models predict the delays of the hardware closely, then the hardware-to-model correlation is said to be good. If, however, the hardware delays don""t match the predicted simulation delays then the hardware-to-model correlation is poor. In actuality, it is not possible to create exact models for delay that match the hardware and sometimes hardware-to-model correlation can be quite bad. This is particularly true with new technologies like silicon-on-insulator (SOI) technology or even with fast versions of traditional bulk CMOS technology.
A critical path simply refers to the slowest path through a circuit and usually starts and ends with a latch boundary, a latch being the hardware to store or evaluate a single bit. Especially with the newer technologies, a critical path can be slower than predicted by the models significantly hampering the maximum performance of the system. All too often, moreover, poor correlation isn""t discovered until testing the hardware after it has been fabricated and then it is too late to change the timing delay. A designer knows that not every signal path is a critical path and in a standard distribution of timing paths of circuits, the critical paths are on the slow end of the bell curve. From experience and computer simulation modeling, moreover, a designer also knows where the critical paths are and delays can be removed or inserted into other synchronizing paths during the design. In cases, however, where one critical path feeds another critical path it is difficult to know which path is slower because of inaccurate modeling. The designer may not know whether to take logic out of one path and place it in the other or vice versa in order to achieve a speedup because the delays cannot be reasonably predicted.
One such technology that is capable of achieving high speeds and high density of electronic components in custom integrated circuit design is dynamic CMOS. Dynamic CMOS differs from static CMOS because whereas static CMOS incorporates pull-up and pull-down transistor networks to calculate whether an input signal is a digital xe2x80x9c1xe2x80x9d or a digital xe2x80x9c0xe2x80x9d, dynamic CMOS uses parasitic capacitance, previously considered detrimental in static CMOS, to advantage. In dynamic CMOS, the output node of a combinational logic gate is precharged to a voltage, Vdd, just prior to the evaluation of the logic function and may be conditionally discharged to ground using only one pull-down network, depending on the particular values of input signals. If the inputs are such that the logic function should be a logical xe2x80x9c0xe2x80x9d, then the pull-down output node turns ON and the precharged voltage is discharged quickly to ground. If the inputs are such that the logic function should be xe2x80x9c1xe2x80x9d, the pull-down output node remains OFF and at Vdd.
Several stages of these dynamic CMOS field effect transistors can be configured into a circuit called domino logic because like a row of closely-spaced dominos which have been stood on end, once a signal enters the first latch the signal quickly propagates or cascades to all other circuit elements in the domino circuit like all the other dominos falling once the first domino has been tipped. The first stage of a domino circuit typically comprises a precharge device, typically a p-type field effect transistor (pfet) whose drain is connected to a pull-down network of n-type field effect transistors (nfets) and an evaluate transistor, typically an nfet whose source is connected to the same pull-down network. Precharge occurs on one phase of the clock, a signal is input, and the evaluate occurs on the other phase of the clock. According to the standard rules of domino logic, an evaluate device is required for the first dynamic gate after a latch in order to ensure that the precharge completes successfully. To prevent a signal from propagating to the next domino stage, the output A of each stage has a static CMOS inverter or equivalent to perform a logic inversion that provides the intended causal evaluation of a cascade of many such stages.
Referring to the figures wherein like numerals refer to the same or similar elements throughout and in particular with reference to FIGS. 1(a) and 1(b), therein shown are simplified block diagrams of two possible configurations of a conventional domino circuit with the same logic function in which one critical path 150 feeds another critical path 160. The circuit of FIG. 1(a) is essentially the same circuit as FIG. 1(b) except that the first gate after latch 118 may be a static gate 120 or a dynamic gate 140. If it is a static gate 120, as in FIG. 1(a), the timing boundary or critical path starts on CLK0110 and ends on SINKA 122. If the gate after latch 118 is a dynamic gate 140, as shown in FIG. 1(b), the timing boundary/critical path starts on CLK0110 and ends on SINKB 144. The designer chooses based on the simulation modeling whether to make the first gate after latch 118 a static gate or a dynamic gate specifically to move the timing boundary between the two critical paths 150, 160. If the designer uses a static gate 120, the designer adds the delay of that gate to the first critical path 150; by using a dynamic gate 140, the designer add the delay to the second critical path 160.
FIG. 2 is a conventional dynamic delay inserted after latch 118 in FIG. 1(b). The output SINKB 144 of latch 118 is input into dynamic gate 140. Dynamic gate 140 comprises a precharge device, pfet P10, and an evaluate device, nfet N10. To prevent cascading onto the next stage, there is a domino inverter INV10. Similarly dynamic gate 126 has a precharge of pfet P20 and an evaluate transistor N20. Inverters INV10 and INV20 are standard elements of domino circuits to buffer dynamic stages. Nfet networks 210 and 220 may perform a logical operation on the input signal SINKB 144. The operation of these domino circuit delays is known in the art and will not be explained here.
If the designer can accurately model the circuit delays, he/she can balance the delay of the two critical paths to maximize system performance. But model simulations are not always accurate and if the designer made the wrong decision as discussed earlier, there would be too much delay in one critical path and less in the other and the error would not be uncovered until the circuit was actually fabricated in hardware. Thus, if the designer opted for the design of FIG. 1(a) but critical path 150 already was the slowest path, the designer only exacerbated the problem and made critical path 150 even slower. If, however, critical path 160 was the slowest path and the designer opted for placement of dynamic gate 140 into critical path 160, the designer also increased the delay and slowed the circuit further.
There is thus a need in the industry to create a programmable timing boundary that can be used in dynamic circuits that can be inserted during the design so that the circuits can be fabricated and the choice of which timing domain to insert the programmable boundary could be determined after fabrication.
These needs and others that will become apparent to one skilled in the art are satisfied by a method to increase the speed of a manufactured electronic system having a plurality of domino logic circuits in which at least one of the domino logic circuits has at least one delay, the method comprising removing the at least one delay from the at least one domino logic circuit and including the delay in an adjacent domino logic circuit.
The invention is further embodied in a method to increase the speed of an electronic system having a plurality of logic circuits, the logic circuits comprising at least two stages: a first stage being on during a first timing domain; and a second stage being on during a second timing domain and the second stage being slower than the first stage, the method comprising moving a programmable hardware timing boundary from the second stage to the first stage.
The invention may also be considered a method to move a timing boundary between two adjacent timing paths; the method comprising: placing a programmable gate at a boundary of the two adjacent timing paths; programming the programmable gate to be included in a first of the two adjacent timing paths; or, alternatively, programming the programmable gate to be included in a second of the two adjacent timing paths; and inputting a first signal to program the programmable gate. The step of programming may further comprise programming the programmable gate to be a static gate when the first signal is high. In an alternative embodiment, the step of programming may further comprising programming the programmable gate to be a first dynamic gate when the first signal is low.
The method may further comprise testing a circuit having the two adjacent timing paths which are critical paths to determine which of the critical paths is the slower; and then inputting the input signal to place the programmable gate in the faster of the two critical paths. The testing may occur when the circuits are in a semiconductor wafer; or when the circuits are mounted on an electronic chip.
The method may also comprise testing a circuit having the two adjacent timing paths which are also critical paths to determine which of the paths is the slower and then inputting the input signal to place the programmable gate into the slower of the two critical paths.
The step of programming the programmable gate to be a static gate may further comprise degating a precharge device and shorting an evaluate device in the programmable gate.
The step of programming the programmable gate to be a dynamic gate may further comprise charging a precharge node with a precharge device in the programmable gate; allowing a first evaluate device in the programmable gate to evaluate a value of an input logic signal; favoring a rising edge of an output signal from the programmable gate; and shorting out a second evaluate device in an adjacent second dynamic gate of the second timing path.
It is further contemplated that the invention is an electronic system comprising a number of domino logic circuits having programmable timing boundaries that can be changed by a plurality of gates, each of which can be programmed to be either a static gate or a dynamic gate.
The invention is also an electronic circuit, comprising: a first stage having a first timing domain; a second stage adjacent to the first stage but having a second timing domain; a programmable gate at a boundary of the first stage and the second stage, the programmable gate capable of being in either the first stage or the second stage.
The electronic circuit may be a logic circuit and the first stage and the second stages may be domino stages. In a logic circuit, the programmable gate may further comprise a program signal to program the programmable gate; a precharge device connected to a clock signal; an evaluate device connected to the clock signal; a logic network to perform a digital operation on a logic signal; and a shorting device connected to the program signal. The programmable gate may further comprise a complementary logic network and whereupon when the program signal is high, the precharge device is degated from the logic circuit and the shorting device shorts the evaluate device, and the logic network forms a static gate with the complementary logic network and the programmable gate included in the first domino stage.
In the logic circuit, whereupon the program signal being high, the precharge device precharges the precharge node, and the evaluate device evaluates a logic output from the logic network which forms a dynamic gate and the programmable gate is included in the second domino stage. The second domino stage may further comprise a second dynamic gate and a second evaluate device in which the programmable gate causes the second evaluate device to be shorted.
The invention may further be considered an electronic circuit having an adjustable timing boundary between two adjacent stages, comprising; means to input a program signal; means to program a delay gate to comprise a first of the two adjacent stages upon the value of the program signal; and means to program the delay gate to comprise a second of the two adjacent stages upon a different value of the program signal.
This invention creates a programmable timing boundary for dynamic circuits such that the designer can take a delay out of one critical path and put it in another on the hardware and is capable of placing the delay so that the dynamic circuit is fastest based on actual hardware data.
This invention provides a programmable timing boundary by creating a new gate that can be programmed to be a static gate or a dynamic gate. Further scope of applicability of the present invention will become apparent from the detailed description given herein. It should be understood, however, that the detailed description and the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only. Various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art upon review of the detailed description.